The Liquid Crystal Display (LCD) possesses advantages of thin body, power saving and no radiation to be widely used in many application scope, such as LCD TV, mobile phone, personal digital assistant (PDA), digital camera, notebook, laptop, and dominates the flat panel display field.
The GOA technology, i.e. the Gate Driver on Array technology utilizes the original array manufacture processes of the liquid crystal display panel to manufacture the driving circuit of the level scan lines on the substrate around the active area, to replace the external Integrated Circuit (IC) for accomplishing the driving of the level scan lines. The GOA technology can reduce the bonding procedure of the external IC and has potential to raise the productivity and lower the production cost. Meanwhile, it can make the liquid crystal display panel more suitable to the narrow frame or non frame design of display products.
FIG. 1 shows a common GOA circuit according to prior art, comprising a plurality of GOA units which are cascade coupled. n is set to be a positive integer, and the GOA unit of the nth stage comprises: a first thin film transistor T1, and a gate of the first thin film transistor T1 is electrically coupled to a forward scan control signal U2D, and a source is electrically coupled to an output end G(n−1) of a n−1th GOA unit of the former stage, and a drain is electrically coupled to a source of a third thin film transistor T3; and a second thin film transistor T2, a gate of the second thin film transistor T2 is electrically coupled to a backward scan control signal D2U, and a source is electrically coupled to an output end G(n+1) of a n+1th GOA unit of the latter stage, and a drain is electrically coupled to the source of the third thin film transistor T3; the third thin film transistor T3, and a gate of the third thin film transistor T3 is electrically coupled to a first clock signal CK(1), and a drain is electrically coupled to a gate of a fourth thin film transistor T4; the fourth thin film transistor T4, and a gate of the fourth thin film transistor T4 is electrically coupled to a source of a seventh thin film transistor T7, and a drain is electrically coupled to a second node P(n), and a source is electrically coupled to the first clock signal CK(1); a fifth thin film transistor T5, and a gate of the fifth thin film transistor T5 is electrically coupled to the first clock signal CK(1), and a drain is electrically coupled to the second node P(n), and a source is electrically coupled to a constant high voltage level VGH; a sixth thin film transistor T6, and a gate of the thin film transistor T6 is electrically coupled to the second node P(n), and a source is electrically coupled to a drain of the seventh thin film transistor T7, and a drain is electrically coupled to a constant low voltage level VGL; the seventh thin film transistor T7, and a gate of the seventh thin film transistor T7 is electrically coupled to a second clock signal CK(2), and a source is electrically coupled to a source of an eighth thin film transistor T8; the eighth thin film transistor T8, and a gate of the eighth thin film transistor T8 is electrically coupled to the constant high voltage level VGH, and a drain is electrically coupled to a first node Q(n); a ninth thin film transistor T9, and a gate of the thin film transistor T9 is electrically coupled to the first node Q(n), and a source is electrically coupled to the second clock signal CK(n), and a drain is electrically coupled to an output end G(n); a tenth thin film transistor T10, and a gate of the tenth thin film transistor T10 is electrically coupled to the second node P(n), and a drain is electrically coupled to the output end G(n), and a source is electrically coupled to the constant low voltage level VGL; a first capacitor C1, and one end of the first capacitor C1 is electrically coupled to the first node Q(n), and the other end is electrically coupled to the output end G(n); a second capacitor C2, and one end of the second capacitor C2 is electrically coupled to the second node P(n), and the other end is electrically coupled to the constant low voltage level VGL.
Furthermore, the first thin film transistor T1 and the second thin film transistor T2 construct the forward-backward scan control unit 100 of the GOA unit; the ninth thin film transistor T9 and the first capacitor C1 construct the pull-up output unit 200 of the GOA unit, employed to output the high voltage level of the second clock signal CK(2) to the output end G(n), and the high voltage level of the second clock signal CK(2) and the constant high voltage level VGH are the same; the sixth, the seventh and the eighth thin film transistors T6, T7, T8 construct the first node pull-down unit 300 of the GOA circuit; the fourth thin film transistor T4, the fifth thin film transistor T5, the tenth thin film transistor T10 and the second capacitor C2 construct the pull-down output unit 400 of the GOA circuit, employed to make the output end G(n) output a low voltage equal to the constant low voltage level VGL. With combination of FIG. 2, the signal (G(1)-G(4) as shown in FIG. 2) outputted by the output end G(n) of the aforesaid GOA circuit is a pulse signal having only one falling edge, which is directly dropped from the constant high voltage level VGH to the constant low voltage level VGL.
In the general liquid crystal display, each pixel is electrically coupled to a thin film transistor (TFT), and the gate of the thin film transistor is coupled to a level scan line, and the drain is coupled to a vertical data line, and the source is coupled to the pixel electrode. The enough voltage is applied to the level scan line, and all the TFTs electrically coupled to the horizontal scan line are activated. Thus, the signal voltage on the data line can be written into the pixel to control the transmittances of different liquid crystals to achieve the effect of controlling colors and brightness. After charging the pixel, the gate of the TFT is off, the Feed through phenomenon due to the capacitor coupling between of the gate and the drain instantly as the gate of the TFT is off. Accordingly, a difference exists between the voltage charged in the pixel and the voltage on the data line. The voltage difference before and after the gate of the TFT is off, the caused feed-through voltage is larger. Although the voltage of the common electrode can be adjusted to compensate this difference, the deviation appears in the process, the larger the feed-through voltage is, the common voltage nonuniformity caused by the process deviation will be more obvious. Therefore, it has significant meanings to reduce the feed-through voltage as the pixel is charged for promoting the display uniformity of the display panel. At present, some of the external integrated circuit (Gate IC) employed for driving the gate can output the output signal waveform having two falling edges to reduce the feed-through voltage but it is not applicable for the GOA circuit. The GOA circuit according to prior art shown in FIG. 1 only can output the output signal having one falling edge. Before and after the gate of the TFT is off, the constant high voltage level VGH is directly dropped to the constant low voltage level VGL. The feed-through voltage as the pixel is charged cannot be reduced, which is bad for promoting the display uniformity of the liquid crystal display panel.